Pulse generator for electric fences

ABSTRACT

A circuit (700) for an electric fence energizer (examples are 6 or 24 Joule versions) which synthesizes a pulse having a raised cosine waveform at a first or bus voltage uses a ferrite-cored output transformer (701) to multiply the voltage of the pulse to the required level. A raised cosine waveform has a low harmonic content and little filtering of high-power pulses is required in order to minimize electromagnetic emissions. On closure of a switch (707) in series with an inductor (705) a first capacitor bank (703) commences charging a second smaller capacitor bank (704) in parallel with the output primary and after the peak of the pulse any remaining charge is dissipated in a resistor (708) with the aid of a saturable inductor (702), acting as a switch. The saturable inductor may be the output transformer itself for lower output energizers. The output exhibits little or any reversal of polarity when matched to its load. The circuit may also be useful for applications such as strobe flashers in aircraft.

BACKGROUND OF THE INVENTION

This invention relates to the field of generation of power electricpulses of low harmonic content suitable for use in the control of fencedlivestock; more particularly to circuits for the generation ofrepetitive pulses having controlled shapes, and has particular but notexclusive application to circuits for energizers for electric fences.

DESCRIPTION OF THE RELATED ART

Wire fences electrified with intermittent pulses of electricity havebeen in wide use in New Zealand since at least the 1950s. This type offence is suitable for enclosing livestock on farms, where theportability of such fences has permitted substantial improvements inmanagement practices such as that of break-feeding a paddock to a herdof cows.

In general the power supplies or energizers used with these fencesconvert a relatively small and steady supply of power into briefimpulses of large power (often several Kilowatts) at a high voltage,typically 5KV or more, by (a) the use of slow charging of a capacitorand then its quick discharge through a gas or solid-state switch, and(b) passing the discharge current through a kind of step-up transformer.This order of magnitude of generated pulse power is required in order tocover an entire farm with a single energizer, and to cope with leakagethat may occur on days when rain or dew causes insulators to exhibitsurface leakage particularly across salt deposits, or when wet grass isin contact with parts of the fence. Energizers may be made to produceanywhere from one or less Joules up to about 25 Joules of energy.

One lead of the transformer secondary is connected to a farm-widenetwork of usually galvanised iron wires forming various fence lines;the other lead is connected to earth where currents due to leakage andcapacitative charging will be found, as well as currents that havepassed through animals that inadvertently touch the wire. As the powerimpulses are widely separated in time an animal or human has time todisengage from the fence wire before a following shock, so these fencesare relatively unlikely to cause death, (as compared to a hypotheticalarrangement using DC current or AC mains, for example).

In their simplest and oldest forms electric fence energizers are notunlike capacitative-discharge ignition systems for internal combustionengines. An electric fence energizer also resembles a low-frequencyradio transmitter in that a source of pulsed electricity is coupled to along aerial. A disadvantage of a simple form of electric fence energizeris that some proportion of the power driven into the fence (which is afunction of proper matching) may be radiated into space aselectromagnetic radiation or interference (EMI). This is also known asradio frequency interference or RFI. Past attempts to minimise thisradiation, in order to comply with laws relating to EMI generallyoperate by filtering out harmonics of the basic pulse. The filtersinvolved must handle the power and voltage levels involved, hence theytend to be expensive and may absorb a substantial proportion of usefulenergy.

There is therefore a need for an improved electric fence energizer whichproduces less EMI/RFI and preferably one which accomplishes this bymeans based on never generating interference, rather than by means basedon heavy filtering, which must be at high voltage and high power levels,and hence would require high-capacity components.

There is also a requirement to ensure that electric fence energizersrevert to a fail-save condition if a fault develops. As one of the mainrisks is that the main discharging switch, generally a siliconcontrolled rectifier (SCR) or thyristor, if it becomes faulty, enters amode in which repeated discharges of powerful pulses may occur even inthe absence of a deliberately generated gate pulse, there is a need toinclude means to minimise stresses on the thyristor(s) in the circuit aswell as to detect such a condition and prevent rapidly repeated faults.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an improved circuitto generate effective electric pulses for use in electric fencinginstallations, and/or an energizer for an electric fence, or one whichwill at least provide the public with a useful choice.

In a first broad aspect the invention comprises a circuit for anelectric pulse generator suitable for use in an electric fenceenergizer, capable from time to time of generating or constructingpulses of power having a controlled shape with a smooth andsubstantially symmetrical outline, comprising means to determine theshape of the pulse when generated at a first low voltage, and means totransform the pulse so generated into a pulse at a second, generallyhigher voltage without substantial alteration to the shape of theinitially generated pulse.

Preferably the controlled shape is substantially that of a raised cosinewave.

In a related aspect the invention comprises a circuit having at leastone first chargeable means connected so as to receive a charging currentfrom a controlled source of electricity and become charged to a firstvoltage, thereby holding an effective charge, at least one secondchargeable means connected in parallel with the first chargeable meansbut in series with a means possessing effective inductance and also inseries with a first switching means, the second chargeable means alsobeing connected in parallel with pulse transforming means, a dischargingmeans in series with a charge-dissipating means and in parallel with thefirst chargeable means, and actuating means to control the switchingmeans, so that in use the first chargeable means may, on closure of thefirst switching means, transfer its charge via the means havinginductance into the second chargeable means and thus into the pulsetransforming means, and shortly thereafter the discharging means willcause the transferred charge to be returned towards thecharge-dissipating means, whereupon any remaining charge within thefirst chargeable means will be substantially dissipated within thecharge dissipating means, so that in use the amplitude of theconstructed pulse has a rising phase in which it rises gradually atfirst, then more rapidly, then slows to a rounded peak, then falls in afalling phase which is substantially a mirror image of the rising phase,resulting in a pulse of substantially smooth shape being generated.

In a subsidiary aspect to the above, the invention includes a circuitwherein the first chargeable means comprises at least one capacitor andhas about twice the storage capacity of the second chargeable means,which also comprises one or more capacitors.

In a second related aspect the invention comprises a circuit in whichthe pulse transforming means is a transformer having a primary:secondaryturns ratio capable of providing pulses at an effective output voltageand which pulse transforming means has a non-conducting ferromagneticcore such as one of a ferrite or an iron dust composition suitable forhigh-frequency use.

In a third related aspect the invention comprises a circuit in which thedischarging means is a saturable inductor in series with anenergy-dissipating means.

Alternatively the invention comprises a circuit in which the dischargingmeans is provided as an intrinsic property of the output transformerwhich is provided with a saturable ferromagnetic core.

As a further alternative the invention comprises a circuit in which thedischarging means is a switch in series with an energy-dissipatingmeans.

In a fourth related aspect the invention comprises a circuit in whichfurther means to shape the generated pulse comprise one or more means toblock the reverse flow of current and thereby minimize reversal of thepolarity of the waveform.

In a fifth related aspect the invention comprises a circuit in whichfurther control means are provided to cause the construction of a pulseto occur in sequence and to minimize the risk of inadvertent generationof spurious pulses, said control means including means to control andmonitor the source of the charging current, means to monitor the amountof charge placed within the first chargeable means, together with meansto initiate a pulse substantially as soon as the charge reaches apredetermined level, and means to cause a pulse to be generated after acertain time even if the predetermined charge is not accomplished.

In a subsidiary aspect the invention also includes means to sense theinstantaneous phase of an alternating-current mains supply in order tolimit the initiation of charging to the zero-crossing intervals of thealternating-current mains supply and means to limit the generation of anoutput pulse to those moments when the alternating-current mains supplylink is in its negative polarity so that in use a rectification meansplaced between the alternating input and the charging DC voltage is in areverse biased state.

In a related aspect the invention provides a circuit for an electricpulse generator capable of generating pulses of power comprising:

at least one first chargeable means connected so as to receive acharging current and become charged to a first voltage, thereby holdingan effective charge,

at least one second chargeable means connected in parallel with thefirst chargeable means but in series with a means possessing effectiveinductance and also in series with a first switching means, the secondchargeable means also being connected in parallel with pulsetransforming means,

a discharging means in series with a charge-dissipating means, beingtogether in parallel with the first chargeable means, and

actuating means to control the switching means,

so that in use the first chargeable means may, on closure of the firstswitching means,

transfer its charge via the means having inductance into the secondchargeable means and thus into the pulse transforming means, and shortlythereafter the discharging means will cause the transferred charge to bereturned towards the charge-dissipating means,

whereupon any remaining charge within the first chargeable means will besubstantially dissipated within the charge dissipating means, resultingin a pulse of substantially smooth shape being generated.

Preferably the chargeable means are capacitors and preferably the firstchargeable means has about twice the storage capacity of the secondchargeable means. Optionally the capacitors may be made up of smallerunits connected in series or in parallel.

Preferably the switching means is one or more solid-state switches ofthe type known as thyristors or silicon controlled rectifiers.Optionally more than one solid-state switch may be used in parallelconfigurations.

Preferably the discharging means is a saturable inductor, thoughalternatively it may be a solid-state switch.

Preferably the means possessing inductance comprises one or moreinductors.

Preferably the pulse transforming means is a transformer having aprimary:secondary turns ratio capable of providing pulses at aneffective output voltage, and preferably the transformer has anon-conducting ferromagnetic core suitable for high-frequency use, forexample a powdered iron core or a core of ferrite.

Optionally the second switching means may be a saturating inductance.Preferably this is a discrete device but for units whose output capacityis smaller it may be an intrinsic property of the output transformer.

In a related aspect the invention is a pulse-generating circuit asdescribed, including further devices to prevent reverse flow of current,or alternatively to allow the reverse flow of inadvertently createdcurrent.

In a further related aspect the invention is a pulse-generating circuitincluding control means to minimize the risk of inadvertent generationof spurious pulses, said means including means to restrict the chargingof the first chargeable means until immediately before a pulse is to begenerated, means to monitor the amount of charge placed within the firstchargeable means, together with means to create a pulse as soon as thecharge reaches a predetermined level, and means to cause a pulse to begenerated after a certain time even if the predetermined charge is notaccomplished.

In a yet further aspect, RFI fed into the main supply is minimized bysynchronising the generation of output pulses to occur during thehalf-cycle of the mains input when a diode placed between thealternating input and the high DC voltage is in a reverse biased state.

Alternatively interference may be minimized by causing-output pulses tobe generated substantially at zero-crossing instants of the supply sothat possible interference is unable to pass through semiconductors whenin a non-conducting state as at such instants.

Alternatively the invention may include control means to restrict thecommencement and the termination of the charging process and the momentof creation of the pulse to occur substantially at zero-crossinginstants of the incoming AC mains so that in use minimal RFI isgenerated and fed into the AC mains supply;

In a third broad aspect the invention comprises a method for generatinga pulse of high voltage having a controlled shape by first generatingthe pulse at a first lower voltage and determining its shapesubstantially at that first lower voltage, and then transforming it to ahigher voltage.

Preferably the controlled shape exhibits smooth outlines and asubstantially symmetrical shape. A preferred shape has a raised cosinewaveform, or a sigmoid curve-like outline, that is, it resembles theshape of a normal-distribution curve, with a gradual commencement and agradual termination.

Preferably the pulse has a duration of approximately 180 microseconds,though the preferred range extends from about double to about half ofthat duration.

In a related aspect the invention comprises a method for generating apulse of a controlled shape including the steps of controlling the rateof rise and the final height of the rising portion of the pulse, from abase level up to a peak amplitude, by passing a charge from a firstcharged electrical storage means into a second uncharged electricalstorage means through a means having inductance and through a switch,and then controlling the rate of fall of the pulse from its peak down tothe basal level by returning the charge from the second storage meansback to the first, now relatively discharged storage means and intocharge dissipating means, with some assistance from resonance effects inthe circuit.

In a supplementary aspect the invention comprises a method of operationof a circuit comprising the steps of: commencing the charging of a firstcapacitor, determining when the charge has reached a predeterminedlevel, discharging the charge through at least one inductor having aselected inductance into a second capacitor of preferably substantiallyhalf the capacitance of the first capacitor, and then shorting out thefirst capacitor until the charge in the circuit has returned to it andbeen dissipated, meanwhile extracting a pulse output from across thesecond capacitor via a primary winding of an optimizing transformerwhich produces an output pulse of a desired voltage, current, andduration.

Optionally the ratio of capacitance of the first and second capacitancesmay be other than two to one.

Preferably the amplitude and duration of the pulse is optimized in orderto provide an effective waveform for use in an electric fenceinstallation.

Preferably the harmonic content of the pulse is minimized in order tominimize spurious radiation of electromagnetic interference. In effectthis means that the pulse changes amplitude at a slowly varying rate,and tends to be smooth and symmetrical.

Preferably means are provided in order to minimize undershooting of thewaveform below the baseline, or a reversal of the original polarity ofthe pulse, even if the impedance of the fence is poorly matched to theimpedance of the generator.

Preferably the instants of commencing the charging process and ofcommencing the pulse formation process are synchronised withzero-crossing instants of the incoming AC mains, in order to minimizeelectromagnetic interference that may be propagated within the mainssupply.

Optionally the invention provides a method for minimising the RFI fedinto the mains supply by synchronizing the generation of output pulsesto lie in the half-cycle when the voltage doubler diode is in a reversebiased state.

Optionally the second switching means may be a saturating inductance.Preferably this is a discrete device but for units whose output capacityis smaller it may be an intrinsic property of the output transformer.

In a further supplementary aspect the invention comprises a method ofpreventing or at least minimising the amount of electromagneticinterference passed from interference-generating equipment through arectifier and back into the mains by synchronizing the times at whichinterference is likely to be generated with zero-crossing instants ofthe mains supply so that interference so generated cannot pass throughthe rectifier elements which are at such instants in a substantiallyhigh-impedance state.

In a related aspect the rectifier elements are preferably of thefast-recovery type having minimal stored charge at or near thesemiconductor junction or junctions, or at least use additionalrectifier elements that exhibit the property of fast recovery.

In a related aspect the invention comprises the above method when usedin an electric fence energizer.

BRIEF DESCRIPTION OF THE DRAWINGS

The following is a description of a preferred form of the invention,given by way of example only, with reference to the accompanyingdiagrams.

FIG. 1: is an oscillogram of a pulse produced by the circuit of thisinvention.

FIG. 2: is a simplified circuit diagram illustrating the principles ofthe present invention.

FIGS. 3a and 3b: are a circuit diagram of an embodiment of the presentinvention.

FIG. 4: illustrates prior art output pulses from two example energizers;both into 500 ohm loads.

FIG. 5: illustrates a pulse train generated by the present invention.

FIG. 6: is a simplified circuit of the pulse generation portion of aprior art energizer (Stafix SM3000)

FIG. 7: illustrates, in simplified form, the saturable inductor versionof a 24 Joule electric fence energizer.

FIG. 8: illustrates, in simplified form, the saturable inductor versionof a 6 Joule electric fence energizer.

FIGS. 9, 10 and 11: illustrate some test results of the noise outputfrom the energizer according to the standard test NZ S3124.1:1993

FIG. 12: illustrates a circuit diagram for the charging portion of anelectric fence energizer, for either 6 or 24 Joules, in which atransformer raises the incoming mains voltage for the internal bus.

FIG. 13: illustrates a circuit diagram for a 24 Joules energizeraccording to this invention, including a saturable reactor.

FIG. 14: illustrates a circuit diagram for a 6 Joules energizeraccording to this invention, wherein the saturable reactor is the outputtransformer.

FIG. 15: illustrates another circuit for a 6 Joule energizer in which adiode multiplier raises the incoming mains voltage for the internal bus.

FIG. 16: illustrates the circuit of the control section for an energizeraccording to FIG. 15.

DESCRIPTION OF THE PREFERRED EMBODIMENT

An electric fence energizer is in principle a device to produce a briefpulse of high-voltage electricity at a relatively high power, useful fordistribution within fence wiring over a wide area such as an entirefarm. We shall outline the principles of most energizers, compared andcontrasted with our circuit and describe some preferred embodiments ofelectric fence energizers.

The preferred operating principle includes storage of a charge ofelectricity in one or more capacitors, building up the charge over arelatively long period, then discharge of the capacitor through a switchand then a step-up transformer primary winding in a relatively shorttime, so concentrating the current and limiting (by virtue of capacitorcapacity) the quantity of electricity in the pulse. This principle isalso widely used in electronic (strobe) flash photography, capacitativedischarge ignition, and the like.

In several ways the design of an electric fence energizer includebalancing a desired effect against an undesired consequence. For examplethe balancing of power output (more is better) against safety (less isbetter), or the balancing of power output against electricalinterference especially radio frequency interference (RFI). Manycountries impose regulatory constraints to provide for safety and lowemissions.

The exponential waveform generated by a simple, prior art capacitativedischarge type of energizer (see FIG. 4) seeking to come close to powerlimits is clearly likely to create RFI/EMI. The harmonic content of thesharp rise to the peak is particularly bad. Prior-art solutions to theRFI problem involve intensive filtering or actual clamping of thisabrupt rise and it is estimated that the added expense and the wastedoutput implicit in such filtering are commonly both of the order of 20%.

Some previous attempts to generate a pulse initially free of harmonicshave claimed to provide a power-handling resonant circuit about theoutput transformer, so that the pulse as generated resembles a sinewave. Some problems associated with that approach include that thebeginning and particularly the end of the pulse possess sharptransitions, that as the main storage capacitor is incompletelydischarged that the circuit may continue to resonate and thereby delivera dangerous train of output pulses, and that high circulating currentsexist

The novel circuit of the high-voltage pulse generator of this inventionhas been developed to construct a substantially symmetrical output pulsethat substantially represents a raised cosine wave, having an effectiveduration and amplitude.

The present invention has been devised for the reliable, high-power,construction of widely separated single shaped pulses, applicable forexample to electric fence energizers. The shape of any one of ourconstructed pulses is that of a raised cosine wave with a gradual onsetand gradual termination of voltage or current; thus the nominally 160microseconds pulse that we prefer to generate has a minimal harmoniccontent above its fundamental "frequency" of around 6 KHz. Thispulse-construction approach minimizes radio-frequency power generationwithout provision of many filtering components which is an advantage, asfiltering a high-power pulse is an inefficient and expensive procedure.

Resonance is not believed to be implicated in the construction of apulse. One trap to inhibit resonance comprises a diode 706 in inverseparallel connection across the inductor 701 (see FIG. 7).

The circuit output is supplied from a finite energy source--a chargedcapacitor--not an infinite energy source such as the mains supply. Thestored capacitor charge sets the output energy of the pulse. It isuseful to completely discharge the capacitor at the end of each pulse,in order to minimize hazards and to maximise the peak energy. In smallfence units (such as the 6 Joule example) we build the outputtransformer so that its core will enter saturation, while in large unitsa separate saturable inductor is preferred as a means to discharge thecapacitor, as in the 24 Joule example.

The capacitance ratio between the storage capacitor 703 and thecapacitor 704 across the inductor 701 is about 2:1. Both capacitors arepreferably non-electrolytic pulse capacitors, typically with apolycarbonate dielectric. The capacitors may be made up from a bank ofindividual units, preferably using 30 μF 1000 V units.

We have further discovered that the use of a preferred powdered-ironcore (or any other high-frequency core material such as most ferrites)in the pulse transformer 701 is advantageous in that the generated pulseis transformed to another voltage without significant deterioration ofthe waveform. Prior art energizers generally relied on laminated irontransformer cores which are relatively expensive and have poorefficiency at higher frequencies--although that may have been one partof a low-pass filtering process. Powdered iron cores are readilyavailable and are generally less expensive than comparable ferritecores.

The output of an electric fence energizer is limited by safetyconstraints enshrined in various legislation, such as (for a New Zealandexample) that the maximum energy is 8 Joules into a 500 ohm load, andthat the amount of electricity (product of current and time) should beless than 2.5 milliCoulombs. In effect, these constraints minimize themaximum voltage. There is a preferred pulse length of about 200microseconds (μS)--determined by effectiveness. Furthermore there islegislation to control the amount of radio-frequency interference (RFI)that can be generated by an energizer, as measured in a standard testjig. These regulations have in the past been difficult to satisfy.

The electric fence energizer of this invention uses as a starting sourceof electric power various alternatives such as battery power, (for whichsections relating to zero-crossing of mains input are clearlyirrelevant) or locally generated power or mains power as convenient, andcomprises:

(a) a controlled rectifier, voltage monitor, and SCR triggering circuitsand triggering monitors, to produce a high-voltage DC charging current;preferably of the order of 800 V for a high-power energizer andpreferably including safety functions which among other things preventrepeated small discharges from being generated--as by a damaged siliconcontrolled rectifier (SCR) having gate leakage, and

(b) a high-voltage pulse generator.

In this specification, we make reference to a pulse and while the actualpolarity as placed on an electric fence, for example, is not importantand may be either positive or negative. We have found it convenient torefer to a positive-going pulse and to talk of an amplitude that risesto a peak from a zero baseline, while the same apparatus can generate anegative-going pulse if the secondary windings of the output transformerare connected in reverse.

PRIOR ART PULSE--GENERATING CIRCUIT

An example prior art circuit is illustrated as FIG. 6; taken from theentire circuit for a Stafix SM3000 circuit diagram. 601 (positive) and602 are inputs from a controlled rectifier/voltage doubler which chargesthe storage capacitor 603 to a significant voltage (about 535 V). Thisvoltage is sensed via a chain of high-voltage Zener diodes connectedbetween line 615 and ground. Other circuitry (not shown) also providesprotection against the production of multiple pulses. When the voltageis sufficiently high to cause current to flow through the diodes, othercircuitry (not shown) causes firing of the silicon controlled rectifier616 and thereby causes the stored charge in 603 to be carried throughthe primary of the laminated-iron transformer 607. A higher secondarypulse is developed in the secondary winding. This is clamped byvoltage-dependent resistors 608, 609, and 610; some current is bled offthrough the series resistor 611 and through the neon lamp 612 to serveas a visual indication of a pulse, and is then fed to the outputterminals 613 and 614. Other kinds of prior art circuit provide furtherfiltering of high frequency components of the pulse with inductors andcapacitors. The voltage-dependent resistors offer only token protectionagainst lightning damage.

EXAMPLE 1

This circuit (as shown in FIGS. 2, 3a and 3b) uses an active componentto discharge the capacitor across the output inductor, and in order tocontrol that active component (a thyristor) there is also some timedelay circuitry and pulse generating means.

The controlled rectifier of this invention includes a novel means forisolation of potential interference from the mains. It is known that asthe alternating voltage applied to a real semiconductor diode changespolarity and passes through zero, the diode enters a non-conductingstate once the applied voltage has come below the forward voltage of thediode. Hence there is a brief period (assuming full-wave rectificationis in effect) during which the rectifier is non-conducting and thereforehas a high impedance, so that the equipment is effectively disconnectedfrom the mains. This invention makes use of this effect by arrangingthat the D-flip flop devices 360, 376, clocked by a zero-crossingdetector (304, 304, 361, 362, 363), initiate the onset of charging andalso the onset of the discharge pulse.

While it is sufficient to place the moment of discharge at or about thezero-crossing moments of the incoming mains supply, the large amplitudesof voltage change occurring within the fence unit may pass through thevoltage doubler diode (325 of FIG. 3a) and the circuitry to determinethe zero-crossing interval is not trivial. Preferably, therefore themoment of discharge is set to occur during the depth of thenegative-going swing of the incoming mains, during which time the diode325 is quite substantially reverse-biased. A simple RC delay deviceprior to the PUT 380 (which triggers the main discharge units) sufficesto provide this delay. A reduction of the order of 60 dB has beenmeasured.

Of course, the effect of stored charge at a P-N junction diminishes theduration of the "window" of high impedance, and for this reasonsemiconductors of the "fast recovery" type in which this stored chargehas been minimized are preferable. Hence, as Triac devices (as 318) haveinherently poor recovery characteristics, a series diode 324 of afast-recovery avalanche type (Philips BYV56) is added.

The novel circuit of the high-voltage pulse generator of this inventionhas been developed to generate a substantially symmetrical output pulsethat closely approximates a raised cosine wave. It is also similar tothe sigmoid curve of a statistical normal distribution curve because thepulse as generated (see FIG. 1) includes a gradual onset and a gradualtermination to the leading and the trailing edge of the pulserespectively, thereby minimizing the harmonic content of the power fedinto the fence. An ideal pulse exhibits a slow rate of change. Furtherminimization of EMI/RFI is implied by the overall symmetry of the pulse.FIG. 1 illustrates a digital oscilloscope recording of such a pulse. Inaddition the lack of undershoot--below the baseline--at either end ofthe main pulse should be noted, for this further minimizes harmonics.FIG. 5 illustrates a series of such pulses as would be generated duringuse. Each pulse is of about 150-180 μS duration and is repeated at about1 second intervals.

FIG. 4 illustrates prior art energizer outputs from two example units,as oscillograms. These pulses are evidently asymmetrical, and have arelatively large rise time, especially at pulse initiation. Asignificant series of harmonics would be obtained if one applied Fourieranalysis techniques to waveforms such as these.

FIG. 2 illustrates the principles of the pulse-generating circuit. Thecontrolled rectifier, being prior art, is illustrated as a block and maybe any source of charging current The circuit of this energizer is bestexplained with reference to its operating sequence.

(1) The preferred controlled rectifier (within the circuit board CB 1)charges the pulse capacitor C1 for which a preferred value for one ofmany sizes of energizer is 130 μF. (This capacitor and C2 are preferablya type of capacitor adapted for pulsed applications.)

(2) From time to time, such as at about one second intervals, a firstSCR, SC1, connected to one end of C1 is caused to conduct.

(3) In contrast to much of the prior art, the rate of rise of dischargecurrent is intentionally limited by (a) the inductor I1 (for which apreferred value is 20 μH) and (b) a second capacitor C2 (preferably thisis half the capacitance of C1 so in this case a value may be 65 μF). Thetime constant of this series-resonant circuit may be adjusted byjudicious selection of inductance and capacitance although the 2:1 ratioof capacitance is to be preferred.

(4) As charge builds up in, and the voltage across C2 rises, currentpassing through the 1:10 step-up transformer T1 rises and the first orrising half of a corresponding output pulse (see FIG. 1) is generated.

(5) At approximately the moment when the voltage across C2 has reachedits peak, a second SCR (SC2) placed across C1 and in series with anenergy-dumping resistor R1, preferably of about 0.4 ohms, is caused toconduct.

(6) This assists the swinging return of charge (including the collapsingflux in the inductor) from C2 back to C1, bypassing SCR 1 through theseries reverse diode D1 and through the closed SCR 2 and theenergy-dumping resistance. Thus the output voltage generated in thesecondary of T2 falls, first gradually as a result of the inductance ofI1, then more quickly, and finally more gradually again as the voltagedifference between C1 and C2 tends towards zero.

(7) In order to compensate for imperfect matching, non-ideal behavior ofcomponents and/or of the electric fence driven by the energizer, anumber of suppressor components are preferably installed. (These areillustrated in FIGS. 3a and 3b). A diode 338 in series with the outputwinding blocks reverse current flow. It may be a 200 V, 3A rectifierdiode, or a zener diode, or a surge arrestor (varistor). A dummy loadresistor 339 of typically 4K ohms across the output incidentally helpsto cause the output to revert to zero in the event of a capacitativestorage of charge in the fence. A diode 388 across the first dischargeSCR 387 helps to block reverse transients, possible if the SCR has (asit should) reverted to its non-conducting state on reversal of itsanode-cathode polarity. A diode 326 across C1 (also 327, 328 in FIG. 3)and a diode 335 across C2 (333) also help trap polarity reversals. Thesecomponents may be termed snubbing components by analogy with the reversediodes commonly placed across inductive loads in order to protect thesemiconductors that switch their currents.

This type of circuit action may be described as a "sequential pulseconstructor" in that it executes a sequential process, involving theswinging of charge from one storage unit to another, then back again, inthe process of constructing a pulse. The rising and the falling portionsare generated by partially separate controllable processes.

It should be noted--in contrast to conventional energizers--that at theinstant of closing the first SCR (SC1) no output is generated. Theoutput builds up gradually, as indicated with reference to the X axis inFIG. 1, as charge is transferred to C2 through L1. In conventionalenergizers an exponentially decaying current builds up rapidly, in thefirst third or less of the duration of the entire pulse.

The step-up transformer T1 preferably is low in inductance andpreferably has a powdered-iron core for the sake of effectiveness,though optionally the core may be of ferrite or other materialsretaining their permeability (μ) at high frequency and so suitable forhigh-frequency use. The transformer is required only to convert thevoltage/current ratio and has a minimal incidental filtering effect. Theμ of a preferred powdered iron core is 75. It has been observed that therelatively expensive laminated steel has a somewhat inferior performancewhen used for pulse transformation at the frequencies--approximately 6KHz--involved. The preferred step-up ratio is 1:10 though other ratiosmay be selected if, for example, it is used in a battery-drivenenergizer. One preferred embodiment uses a powdered iron core, typeE405/40 from Micrometals, Anaheim, Calif. It has 32 turns in the primarywinding, 352 turns on the secondary winding, and the primary inductanceis 500 μH.

In use, this circuit has been found to produce pulses of substantiallysimilar shape when driving loads from even as low as 10 ohms up throughthe target value of 500 ohms and up to impedances at which the internalload resistor becomes the dominant loads

Additionally, any solid-state switches (SCRs and the like) in thecontrolled rectifier circuit are preferably triggered when the inputmains voltage passes through zero-crossing instants; having theadvantage of further minimising RFI.

THE PULSE--GENERATING CIRCUIT IN MORE DETAIL

This discussion relates to the pulse circuit forming the top section ofFIGS. 3a and 3b. Note that the diagram is divided in two, and lineslabelled A.E in each half correspond to the severed lines. At the leftside (FIG. 3a) are mains input connectors 301, and at the right side ofFIG. 3b are the two pulse output terminals.

Incoming mains power is fed past a surge arrestor 302 (275 V) and aspike-filtering capacitor 303 (47F), across a 12 V zener 305 in serieswith a 270K resistor 304, used to develop half-cycle pulses forzero-crossing synchronisation on the control circuit. A 100K bleedresistor 306 is provided in case of parts failure. The control board(lower part of FIGS. 3a and 3b) requires a 12 V supply and this iscreated from the mains by tapping current through 307 (390 ohms), 308,(0.22 μF), and rectifying the current with diodes 309, 310, and clampingit to 12 V (after filtering with 309(0.22 μF, 311 (470 μF)) with a zenerdiode 313.

The mains power is then rectified in a controlled-rectifier voltagedoubling circuit. It passes through a capacitor 314 (4μF) and seriesresistor 315a (60 ohm 10 W) to the rectifying diodes 317,325(fast-recovery BYW56); where 317 is in series with a controlledrectifier or Triac 318 (type BT138-800) used as a solid-state switch forthe charging of the main storage capacitor.

At this point the drive circuit for the controlled rectifier should benoted; it comprises a gated oscillator (Schmitt buffer 342--1/8 40106together with feedback loop of 348 (220K), 347 (10K) and diode 346,1N4148; driven through buffer 341 (1/4 4001), in series with diode 344,a 1N4148) which turns the FET ON with a further pulse every 100microseconds (during the required period); thereby minimising RFIgeneration from the energizer into the mains input as could occur fromTRIAC circuits driven with just a single brief pulse per mains cycle.

The anode of diode 325 (BYV56) represents a point at which a chargingcurrent at up to at least 750 V, developed from the mains by the circuitdescribed above, is provided to the pulse generator of this invention.

The storage capacitor (as C1 of FIG. 2) is here represented by a pair ofsuitably rated 65 μF pulse capacitors, 327, 328 in parallel, and a diode326 (6A10) in reverse across them (to trap undershoots). To the left ofthese capacitors is the means for dumping remaining charge andterminating the output pulse--corresponding to SC2 and R1 of FIG. 2. Inpractice, inductor 323 (10 μH) is used to limit dI/dt--the rate of riseof current through the SCR 322--type S4616NJI, and resistor 324--0.4ohms--dissipates the unwanted energy.

The resistor chain 329 (270K, 1%), 330 (330K, 1%), 331 (100K--1%) and332 (4K7--1%) provides a sample of the charge voltage to avoltage-sensitive discharge triggering circuit.

The return line of the circuit now passes through a paired set ofdischarge SCR devices, (in parallel to share the peak currents involved)387, 387a which are type S4616NJI. Resistors 389, 389a (3 ohms), and390, 390a (100 ohms) provide gate current limiting and return paths forany gate charge. The reverse diodes 388, 388a (type 6A10 rated at 1KV)allow the 65 μF capacitor C2 (333) to discharge and thereby generate thefalling half of the pulse. Inductors 385, 385a--each being 40 μH--serve(a) to force sharing of current through the paired paths, and (b) arethe inductance shown as L1 in FIG. 2, for a combination of limitingdI/dt in this circuit and providing a resonant tank circuit.

Sampling diodes 386, 386a detect a triggered pulse and the bufferingsource-follower FET 393 (BST100) relays this information to the controlcircuit.

Capacitor 333 is a single 65 μF pulse capacitor, thus providing thepreferred 2:1 ratio described with reference to FIG. 2. Across thiscapacitor are: a damping resistor 334 (3.3 ohms), transient-trappingdiode 335 (type 6A10), and the 500 μH primary of the low-inductance 1:11ratio powdered-iron cored step-up transformer 336.

Finally, the generated pulse may be modified by passing it through adiode 338 (type BY329-120S--a 250 V type protected by a surge arrestor337 in parallel, and a damping resistor 339 (10K) is placed across theoutput terminals 340. The diode in particular serves to minimizeundershoot.

THE CONTROL CIRCUIT IN MORE DETAIL--FUNCTION

The way in which this circuit--in particular referring to the fullcircuit in FIGS. 3a and 3b also indicated as the box CB1 in FIG.2--operates is as follows:

(1) After firing of a pulse the bidirectional controlled rectifierswitch 318 is held open for a period determined by a timing circuit(364,365 and associated parts).

Thus no charge is applied at this time to the main storage capacitor(C1, or 327-328).

(2) When the timing circuit changes state, the controlled rectifier,which actually forms part of a voltage doubler circuit around the Triac318 is closed and a charge is built up in the main capacitor.

(3) Meanwhile a sample of the rising voltage across the capacitors issampled from the resistor chain 329,330,331,332 and compared against 6volts from a reference zener diode 375 by the comparator 374.

(4) When the comparator recognises equality and changes state, the pulsegeneration sequence is initiated at the next zero-crossing instant ofthe mains supply, and the controlled rectifier is also turned off via393 and the bistable latch 358,359.

(5) In case of diminished mains supply or a voltage doubler fault,causing the rising voltage to be unable to reach the target value of 750V, the timing circuit output is also fed across via the NOR gate 377 tothe programmable unijunction (PUT) transistor 380 and causes it to emita pulse which fires the main discharge SCRs 387, 387a, even though theoutput pulse will be of a lower than intended value.

Thus the main capacitor is not left in a charged state over a longperiod during which false triggering might occur. Furthermore each pulsecarries the same amount of charge as a constant-charge triggering pointis ensured as described herein, to initiate discharge.

THE CONTROL CIRCUIT IN MORE DETAIL--STRUCTURE

Considering FIG. 3a first and taking the above pulse-handling circuitdescription as read; The leftmost line takes mains-synchronous pulsesvia a limiting resistor 361 (33K) to a chain of Schmitt inverters (362,363) in order to generate clock signals to drive D-flip flops 360, 376(type 4013). The purpose of this section is to cause the controlledrectifier to act at zero crossing of the mains supply and therebyminimize RFI generation at the Triac.

The oscillator to drive the Triac has been described above. It is causedto act by a signal from the bistable latch constructed from gates 358,359; (1/2 4001) which is set OFF by a signal from the pulse-detectingFET 393, and set ON by buffered output from the conventionalfree-running pulse generator circuit of inverting buffers 364, 365, inwhich capacitor 369 (1 μF) and resistors 366, 367 (560K, 470K) set acycle time of approximately 1 second. This timer initiates a pulsegeneration sequence by causing the storage capacitors to become charged.

This timer also causes a pulse to be generated in any case (even in theabsence of sufficient charge voltage) through its output being coupledvia D-flip-flop 360 to the NOR gate 377 which drives the PUT 380(2N6027) which is the only route for triggering the main discharge SCRs,387, 387a. The PUT dumps charge from the capacitor 381 (0.47 μF) builtup from 12 V applied across a resistor chain 379(47K) and 382 (68K) intothe SCR gates.

The comparator (374) circuit, which compares a fraction of the maincharge voltage with the voltage across a 6 V reference zener (375) inseries with a resistor 384, also includes protective diodes 372 and 373(1N4148).

Finally, discharge of the charge-dumping SCR 322 is caused by thenetwork around PUT 353 (2N6927), in which a triggering pulse formed atthe moment of discharge of the main SCRs, 387, 387a is coupled through aRC delay (350; 1K, 351, 1.2K, 352, 160 nF) to the PUT. This gives a timedelay of 80 μS to the discharging portion of the sequence whichcorresponds to the peaking of the waveform.

Advantages of this entire circuit for an electric fence energizerinclude that:

(1) The shape of the output pulse is idealized, as a raised half cosinewave, and substantially matches the low-voltage pulse as generated.Little or no filtering of the pulse once it exists at high voltagelevels is required. This results in less wasted power and the energizerneeds no expensive filter components.

(2) The peak current flowing through the SCRs 822, 822a is limited,typically to 500 A and has a gradual onset; whereas prior art energizercircuits of similar output power levels may impose instantaneous 1500Apulses that have presented a particular challenge to SCR manufacturers.

(3) Powdered iron step-up transformers are cheaper and more efficientthan lamination-based transformers.

(4) Novel means to effectively limit RFI from being propagated throughthe mains supply are included.

(5) Attaining suitable output levels in an efficient and reliable wayfollows from the above advantages.

EXAMPLE 2

This circuit (as shown in summary in FIGS. 7 and 8, and in detail inFIGS. 12 to 16) uses a passive component to discharge the capacitoracross the output inductor, and thus there is no need to providepulse-generating means in order to construct the falling part of theoutput waveform.

This modification to the circuit of Example 1 replaces the chargedumping semiconductor of (5) above--i.e. thyristor 322 and itstriggering circuit about the PUT 353--with a saturable inductor 702,connected as shown in FIG. 7 across the primary winding of the outputtransformer 701, although in units having smaller outputs (e.g. 6 Joulesrating) it may be set up as shown in FIG. 8 where the output transformeritself is designed to become saturated and thereby discharge thecapacitor across it. (In designing prototypes of larger units we havefound that saturation of the main transformer overloads othersemiconductors, though design or component improvements may overcomethis).

A preferred saturable inductor 702 for a 24 Joule unit comprises an E225core of powdered iron. Its windings comprise a pair of 50-turn windingsof about 1 mm insulated wire connected in parallel and wound on a splitbobbin. This exhibits an 11:1 ratio of inductances; 500 μH belowsaturation and 40 μH above. (The primary of the output transformer isalso about 500 μH).

Construction of an output pulse proceeds as follows:

The two capacitor banks--as for the description of Example 1--allow thecharge first placed in 703 to swing across to 704 when the thyristor 707is closed, while the rate of rise is limited by the series inductor 705and the slowdown at the peak is caused by approaching equality of chargevoltage. Once the charge reaches the peak voltage the saturable inductor702 becomes saturated and its much lowered inductance allows a greaterflow of discharge current to pass through it and the series dumpingresistor 708, so that the voltage across the output transformer primarynow begins to fall and continues to fall until it reaches substantiallyzero output. The onset pf the fall and the termination of the fall areagain controlled by circuit parameters at the beginning and the approachof the charge to zero volts at the end of the pulse.

The provision of a parallel pair of windings (not shown in the circuitdiagram) within the discrete saturable inductor provides redundancy incase of failure of one winding, in order to meet the test requirementsfor fence units which include a requirement that deletion of anycomponent shall not put the unit in a dangerous state. This passivecomponent does in any case have a higher reliability than thealternative of Example 1, using thyristor 322, and precise timing of itsgate pulse is not an issue if a saturable inductor is used instead.

An electric fence energizer according to this circuit may also includeextra features such as audible and/or visual indications of outputpower.

FIGS. 9, 10, and 11 illustrate the results of tests carried out at atest laboratory (IRL) in Christchurch in accordance with the standardtest NZ S3124.1:1993. FIG. 9 illustrates the "Load noise" test; a graphof frequency distribution (from 0-30 MHz) of emitted noise into aprescribed test load, (as per CISPR clause 5.3.6) in relation to apermitted output. It can be seen that the addition of a 10 nFhigh-voltage capacitor across the output terminals brought the emittedRFI below the permitted limits at the low end of the frequencyspectrurm. FIG. 10 illustrates the RFI fed into the phase lead of themains input Here it can be seen that a 0.33 μF capacitor across theinput further reduced the RFI emitted by the circuit. FIG. 11illustrates the RFI emitted into the neutral lead of the mains circuit,and again this is substantially below the permitted limit, particularlywith the addition of a 0.33 nF capacitor.

Details of a more preferred circuit (including saturable inductors) forenergizers of both 6 and 24 Joule capacity are now discussed, mainlywith reference to differences over the earlier circuit. FIGS. 12, 13,14, 15 and 16 apply. These circuits include some duplication in order toseek fail-safe operation.

MAINS--INPUT POWER SUPPLY

FIG. 12 illustrates an example power supply section, taking input fromthe mains (at 121, 122) and when enabled, generating about 750 V at itsoutput--the point labelled H, K for the purpose of charging the pulsecapacitors. The input section includes a fuse 123, series resistor 124,surge arrestor 125 and a transient filter 126, and passes the mainsthrough a step up autotransformer 127 which has a first output of about350 V RMS and a second isolated output of about 15 V RMS. A transformermay be preferred in this example particularly for use in countries with117 V mains supplies to provide a high enough working voltage. (Example3 uses a diode multiplication chain instead). The 15 V output is takento a sub-circuit (not shown) at 1259 which generates 12 V DC for thecontrol circuitry using a conventional rectifier, three-terminal 12 voltregulator, and filtering capacitors.

Connectors 1221 (12 V supply, 1222 (enable charging of main capacitors)1227 (gate of SCR), 1228 (zero-crossing of mains signal from withindoubler), 1260 (zero-crossing of mains signal from transformer) and 1232(ground) are connected to a control board similar to that of FIG. 16.

Connectors 1238 and 1246 are linked to a separate winding on the outputtransformer and are coupled to three dividing circuits which areconnected to a display circuit showing the output level. (In the 6 Jouleenergizer which has a simpler display, connectors 1252 and 1258, and theassociated circuits are not provided.)

24 JOULE CIRCUIT

FIG. 13 illustrates the pulse generation circuitry (as a non-limitingexample) for a 24 Joule unit. Charging current at a voltage of about 750V is provided from time to time to point H from the circuit of FIG. 12.Capacitors 135, 136, 137, 138, 139, and 1310 are the main storagecapacitor (cf 703 in FIG. 7) and capacitors 1313, 1314, and 1315correspond to 704 of FIG. 7. Note that the ratio of capacity of therespective capacitor banks is approximately 2:1--as also in FIG. 14. Theprimary of the iron powder-cored step up transformer (not shown) isattached to connectors 1320 and 1321. Preferably a 10 nF capacitor isconnected across the output of this transformer in order to minimiseradiated RFI, and optionally means to protect the energizer against theeffects of lightning strike may also be included.

A low-resistance high-power resistor (or preferably a pair of such inparallel) is placed between points 1312 and 1323 to dissipate theremains of the charge and this corresponds to 708 of FIG. 7. Thesaturable inductor 1311, which serves to dump the remaining charge inthe capacitors corresponds to 702/FIG. 7 and it preferably includes apair of windings in parallel. 1322 (cf 705) limits the rate of rise ofthe pulse waveform. The pair of thyristors 1326 and 1327 (preferablytype S4016NH and corresponding to 707 of FIG. 7) are turned ON by adrive pulse from the control board, via connector 1332 (corresponding toline 710). Diodes 1328 and 1329 (see 706 of FIG. 7) trap any tendencyfor resonant currents to oscillate to and fro in either capacitances1313, 1314, 1315 with inductance 1322, or with the output transformer.Diodes 133, 134, and also diodes 1316 and 1317 also suppress reverseflow and thereby serve to construct the termination of the pulseproduced by this energizer. Connector 1325 monitors the action of themain thyristors, while 1318 and 1319 are for monitoring the DC bus forthe presence of a charge.

6 JOULE ENERGIZER

FIG. 14 illustrates one example circuit (corresponding to FIG. 12 andFIG. 13) for a 6 Joule unit, to be connected to the power supply of FIG.12 at K, in which the step-up or output transformer itself is designedto become saturated and thereby have the effect of discharging thecapacitor and causing the downward slope of the constructed pulse. Thus1311, and the resistor between 1312 and 1323 of FIG. 13 are notprovided, and the other semiconductors are not duplicated. In this casethe capacity of the main storage capacitor 147 and 148 is about onequarter of that of FIG. 13, thus giving about one quarter of the storedcharge of the 24 Joule unit. The capacity of the secondary capacitor1410 is reduced in proportion. Other components may be matched byposition.

    ______________________________________                                        Table of parts values, for FIGS. 12, 13 and 14.                               (Cnn. = Connector)                                                            ______________________________________                                                      FIG. 12                                                                  121  Cnn. PD1                                                                 122  Cnn. PD2                                                                 123  fuse                                                                     124  2R7-2W                                                                   125  Varistor 275 V                                                           126  0.1 μF                                                                127  Transformer                                                              128  330K                                                                     129  0.1 μF                                                                1210 180K                                                                     1211 6 μF                                                                  1212 47R-5W                                                                   1213 47R-5W                                                                   1214 BYW56                                                                    1215 12R-5W                                                                   1216 Labels                                                                   1217 270K                                                                     1218 BYW56                                                                    1219 3R3                                                                      1220 3R3                                                                      1221 Cnn. J1                                                                  1222 Cnn. J2                                                                  1223 1N4007                                                                   1224 BT139-800                                                                1225 3R3                                                                      1226 3R3                                                                      1227 J11                                                                      1228 J13                                                                      1229 S4016NH                                                                  1230 BYW56                                                                    1231 100K                                                                     1232 J2, J3 = reference                                                       1233 1N4148                                                                   1234 1N4148                                                                   1235 1N4148                                                                   1236 1N4148                                                                   1237 internal ground/reference                                                1238 Cnn. PD5                                                                 1239 1N4148                                                                   1240 10R                                                                      1241 100K                                                                     1242 1 μF                                                                  1243 47K                                                                      1244 Cnn. J5                                                                  1245 Cnn. J4                                                                  1246 Cnn. PD6                                                                 1247 1N4148                                                                   1248 10R                                                                      1249 330K                                                                     1250 10 μF                                                                 1251 680K                                                                     1252 Cnn. J6                                                                  1253 1N4148                                                                   1254 10R                                                                      1255 330K                                                                     1256 10 μF                                                                 1257 680K                                                                     1258 Cnn. J7                                                                  1260 Cnn. J10                                                                      FIG. 13                                                                  131  BYW56                                                                    132  100R                                                                     133  6A10                                                                     134  6A10                                                                     135  30 μF                                                                 136  30 μF                                                                 137  30 μF                                                                 138  30 μF                                                                 139  30 μF                                                                 1310 30 μF                                                                 1311 L1 (see text)                                                            1312 Cnn. JR1 to resistor                                                     1313 30 μF                                                                 1314 30 μF                                                                 1315 30 μF                                                                 1316 6A10                                                                     1317 6A10                                                                     1318 Cnn. J14                                                                 1319 Cnn. J15                                                                 1320 Cnn. PD3                                                                 1321 Cnn. PD4                                                                 1322 40 μH                                                                 1323 Cnn. JR2 to resistor                                                     1324 BYW96E                                                                   1325 Cnn. J8                                                                  1326 S4016NH                                                                  1327 S4016NH                                                                  1328 6A10                                                                     1329 6A10                                                                     1330 3R3                                                                      1331 3R3                                                                      1332 Cnn. J9                                                                  1333 100R                                                                          FIG. 14                                                                  141  Cnn.                                                                     142  Cnn. J14                                                                 143  Cnn. J15                                                                 144  BYW56                                                                    145  100R                                                                     146  6A10                                                                     147  20 μF                                                                 148  20 μF                                                                 149  Cnn. PD3                                                                 1410 20 μF                                                                 1411 6A10                                                                     1412 Cnn. PD4                                                                 1413 40 μH                                                                 1414 BYW96E                                                                   1415 Cnn. J8                                                                  1416 Cnn. J9                                                                  1417 6A10                                                                     1418 S4016NH                                                                  1419 3R3                                                                      1420 100R                                                                     1421 Ground/reference                                                ______________________________________                                    

EXAMPLE 3

Another 6 Joule Energizer

Referring to FIG. 15, showing the 6 Joule energizer 150; the mains inputis applied to connectors 151 and 152, with 152 preferably connected tothe neutral line B. The energizer can be regarded as being made of twoparts:--one being means to provide a suitably controlled and limited DCcharging current to capacitors across a line leading to outputconnectors 1511 from time to time, and the other being means todischarge those capacitors in a controlled fashion. Much of the apparentcomplexity of this circuit results from implementation of means tosatisfy both safety standards and electromagnetic emission standards,though at the same time the improvements assist effectiveness. Safetystandards require provision of a fail-safe circuit incapable ofproducing a life-threatening output (such as a raised dischargefrequency) regardless of failure of any part. Accordingly there isfrequent duplication of components and of functions.

The primary of the output transformer as previously described isconnected to 1515 and 1516. A feedback winding on the power transformeris connected at connector 1559 to the control card, and a status displayis connected to 1558. The control card, FIG. 16, is connected to a12-pin connector 1560 and provides a number of control functions whichwill be discussed below.

Pulse Shaping Components

Components particularly relating to the waveform control aspect, for thepulses developed by the energizer of this invention are at the top rightof FIG. 15 and include:

(A) 1545 and 1546, primary charge storage electrolytic capacitors acrossthe DC bus and the earth or reference line which store the energy priorto discharge in a manner analogous to Cl of FIG. 2. While two capacitorsin parallel are shown here, a greater or lesser number may be used forpragmatic reasons such as availability, compaction, or adjustment ofcapacitance,

(B) the SCR 1549, closure of which initiates the discharge,

(C) capacitor 1513 (analogous to C2 of FIG. 2) and preferably of abouthalf the capacitance of the combination of 1545 and 1546 which absorbsthe "rebound",

(D) diode 1514 which conducts at the end of the rebound and traps anysignificant excursions of the energizer output otherwise likely to gobelow the baseline,

(E) diode 1550 which traps any momentary reversals of potential on thebus, and

(F) inductor 1547 which limits the rate of rise of the primary currentIn this relatively small energizer the core of the output transformeritself is saturable.

Providing Charging Power

The circuit of FIG. 15 provides means to raise a nominally 110 volts ACmains input to a higher voltage, so that the energizer can be used in agreater range of countries. The mains supply connected at 151 haspossible transients (from either direction) trapped in thevoltage-dependent resistor 153 and is passed through a fuse 154 to thecircuit.

Low-voltage split-polarity DC is supplied to the status display viaconnector 1558 from the internal power supply comprising diodes 1517,1518, zener diodes 1519 and 1556, and capacitors 1520 and 1555--thelatter providing a negative polarity.

Low-voltage DC for the control board of FIG. 16 is generated within thesupply including diodes 1522, 1523, with zener diode 1524, and capacitor1525. Both low-voltage supplies are driven from the mains via couplingcapacitors 155 or 156.

A low-voltage signal carrying mains zero-crossing information isdeveloped by crossed diodes 1528 and 1529 in series with a resistor 1527across the mains supply. Another similar circuit (comprising diodes1530, 1531 and resistor 1527 joined to the TRIAC device 1534 indicatesto the control circuit whether the TRIAC is open or closed. Thesedevices may fail in the "closed" state and in this circuit that wouldresult in constant provision of a charging voltage.

Resistor 157 serves to limit the peak charging current intended for 1445and 1546. It is in series with the mains input and a controlled voltagetripler arrangement (diodes 1510, 1512, 1511 and 1538 together withcapacitors 158, 1537 and 159, which is controlled by the TRIAC 1534.Only when 1534 is closed can the multiplier diode chain be activated andprovide power. This diode chain can be called a "Controlled QuadDoubler". Control of TRIAC 1534 provides the control board with theability to limit the duration of charging of 1545 and 1546 so that theenergizer can emit pulses during only a limited period.

Resistors 1535 and 1536 limit the gate current of TRIAC 1534 and providea return to ground for any remaining or leakage current

The duplicated resistor networks 1539 with 1541 and 1542, and 1540 with1543 and 1544 serve to sample the voltage on the DC bus. The duplicateddiodes 1553 and 1554 allow the control board to detect negative-goingexcursions of the output.

Resistors 1551 and 1552 limit the gate current supplied to the dischargesilicon controlled rectifier (SCR) 1549 and provide a return to groundfor any remaining or leakage current.

Control Circuit

This circuit 160, shown in FIG. 16, is intended to provide a repetitivesequence of control signals to the main board and also to monitor for atleast some fault conditions.

The normal sequence of operations is that from time to time a clockpulse initiates a charging sequence in which a state of full charge iscaused and then sensed. This sets off the discharge solid-state switchQ1, hence the energizer emits a pulse.

The timer circuit (an oscillator/divider type 4040--1612 with resistors169, 1611 and capacitor 1610) generates a periodic clock signal at itsQ14 output, buffered through 1615. One branch which is passed through1616, a diode 1618 forming part of an OR gate, and transistor 1625,causes the main charge TRIAC (1534) to close and start charging thecapacitors. 1621 is a connection to the control board power supply(168).

Completion of charging to a desired level--a process which may take0.5-1.5 seconds approximately--is sensed by a comparator comparing thevoltage across a reference diode with that of the bus A. This circuit isduplicated to minimize the risk of failure.

A resistively divided fraction of the bus voltage is provided at pin 5(& 4) of the conenctor 161 to the control board, where it is filteredwith resistor 1662 (& 1677) and capacitor 1663 (1678), and comparedwithin the amplifier 1669 (& 1682) against the voltage across areference diode 1666 (& 1681). The amplifiers have positive feedbackthrough resistor 1667 (& 1683) and diode 1668 (& 1684). The output,which on going positive signals a sufficient charge is taken through alink 1670 (& 1671), to an OR gate diode 1619 (& 1620) and to the base oftransistor 1625 via a threshold-setting zener diode 1623. The output isalso used to inhibit the charging current after passing through 1672(which combines both signal paths), buffer 1673, OR gate 1637, and diode1635. OR gate 1637 is used to include a disable-charging function oncethe clock signal has reverted to its LOW state.

We prefer to cause the SCR and the TRIAC drives (FIG. 15) to changestate only when the incoming mains supply is at zero (or substantiallyso; twice per cycle) so that transient emissions down the mains inputlead are minimized. Accordingly a signal carrying zero-crossinginformation is created within the circuit of FIG. 15--linked to pin 10of connector 161 through resistor 1654 to amplifier 1656 (wired for highgain) and buffer 1657 (which as a Schmitt trigger improves thetransition speed of the signal), then 1660 and 1661 acting as ahalf-wave rectifier for the pulses. The resulting pulses are split; somepulse current goes through 1653 and 1629 to the diode OR gate at thebase of transistor 1625 while the remainder passes through resistor 1636to the trigger of programmable unijunction transistor 1633. A timeconstant about this device, of nominally 700 mS, assists in minimizingthe risk of rapid firing by the energizer.

A second zero-crossing sensor, sampling voltage from across the TRIACswitch of FIG. 15, is connected through line 9 of connector. 161 to asecond "pulse extraction device" incorporating amplifier 1647 withsupporting components, which is however wired in inverse polarity to thefirst "pulse extraction device" because one Schmitt buffer stage isabsent from this second chain. The output from buffer 1650 is summedwith that from buffer 1660 at the junction of diodes 1652 and 1653.

DC power to run the components on the control board is provided at thetop left corner, where zener diode 163 shunt-regulates incoming DC(through current-limiting resistor 164) and the capacitors 162, 165, 166and 167 smooth the power and provide local reserves of current about thecircuit board.

The operation of the circuits of Examples 2 and 3 may be summarized inthese steps--assuming that the equipment is connected and powered up--:

(1) after a certain time, typically 1 second, (as determined principallyby the oscillator 1612, the output of which is logic-gated for enablingor disabling purposes in relation to safety) instigating a charge of themain capacitor bank by turning on the TRIAC 1224 of FIG. 12 or 1534 ofFIG. 15 and (for FIG. 12) at the same time turning ON the thyristor1229. Diode 1218 in FIG. 12 is particularly useful for concealing theslow turn-off transients generated within the TRIAC 1224.

(2) When the charge on the capacitor bank has reached a suitable value,as detected by the duplicated voltage-sensing circuits connected withresistive dividers to the DC bus (ICs 1669, 1682 and reference diodes1666, 1681), the discharge thyristor (1326/1327, 1418, or 1549) iscaused to come ON as a result of gate current supplied from theprogrammable unijunction transistor (PUT) 1633 of FIG. 16. In moredetail a mains phase-determining circuit fed with zero-crossing orpolarity-indicating pulses from line 1526, so that an output pulse isdelivered within a period when the mains input is negative so that therectifying diode 1214 (or the multiplier chain 1510, 1511, 1512, and1538 is substantially reverse-biased so that interference from the pulseis blocked from entering the mains supply.

(3) The actual generation of the raised cosine wave has been describedpreviously.

(4) The circuitry (IC 1647 with ancillary components) connected to thediodes 1530/1531, or to connector 1228 senses the action of the TRIACcontrolling the mains rectifier as a further safety feature, and isprovided to protect against continued re-triggering action of thevoltage-doubling circuit which might happen if the bus was permanentlypowered and the capacitors were usually in a charged state.

(5) The circuitry connected to 1553/1554, to 1414, or to 1324 senses theaction of the main thyristor(s) as a further safety feature and isprovided to protect against failure of these devices to fire normally.

(6) A display board is provided in the case of the more powerfulenergizer, for the purpose of indicating the approximate deliveredpower. Inputs PD5 and PD6 are fed through three scaling circuits toprovide low, medium, and high power level indication. A suitable displayboard has a light-emitting-diode type output.

These detailed circuits are provided by way of example only andrepresent one implementation of the principles expressed in FIGS. 7 and8. Parts values for FIGS. 15 and 16 generally correspond to those forFIGS. 12, 13, and 14, or are commonplace variants such as integratedcircuits of the well-known CD. or HE. families.

The circuit(s) described herein may be packaged in a secure box andprovided with connectors for joining to earth and the electric fence,and a cable to the mains supply. An optional indicator indicates theamplitude of the output pulse and so whether the energizer is drivinginto a partially shorted load (as with wet or defective insulators) or anormal load.

A variant having a clock section which causes the energizer to generatepulses in a pseudo-random fashion; that is, not at a set rate of say oneper second but at any time between a first minimum safe period and asecond maximum effective period may be more use in deterring some typesof animal from rushing the fence.

When variants of these circuits are not powered from the AC mains, butfrom other sources, modifications may be made to the means forgenerating a high DC bus voltage of the order of 750 V. For example aboost DC to DC converter stage may be provided if the circuit is runfrom a battery source. If the device is operated from a 400 Hz supply asgenerally used in aircraft, some parts values may be changed to optimiseits operation at this frequency.

Other possible applications for this type of circuit outside electricfence energizers include: firing xenon flash lamps where on-boardaircraft radio beacon receivers in particular would benefit from the lowharmonic content of the pulse, and some types of pulsed motor drive.

Finally, it will be appreciated that various alterations andmodifications may be made to the foregoing without departing from thescope of this invention as claimed.

We claim:
 1. A circuit for an electric pulse generator suitable for usein an electric fence energizer, capable from time to time of generatingor constructing one or more substantially unipolar pulses of powerhaving a controlled shape, comprising a control means capable ofinitiating and controlling the generation of a pulse, a shaping meanscapable of determining the shape of the pulse when generated at a firstlow voltage, wherein the amplitude of the pulse has a rising phase inwhich it rises from a base level up to a peak amplitude gradually atfirst, then more rapidly, then slows to a rounded peak, then falls in afalling phase which is substantially a mirror image of the rising phase,so that a smooth and substantially symmetrical pulse outline isgenerated; and a pulse transforming means to transform the pulse sogenerated into a pulse at a second, generally higher voltage withoutsubstantial alteration to the shape of the initially generated pulse. 2.A circuit as claimed in claim 1, wherein the shaping means comprises acircuit for generating a pulse having a controlled shape as claimed inclaim 1, wherein the rising phase and the peak amplitude are controlledby passing a charge from a first chargeable electrical storage meansinto a second chargeable electrical storage means, which is initiallyuncharged, through a means possessing effective inductance and throughthe pulse transformer means and through a first switching means, andthen controlling the rate of fall of the pulse from the peak amplitudedown to the base level by returning at least a part of the charge fromthe second storage means back to the first, now relatively discharged,storage means and into a charge dissipating means, whereupon anyremaining charge within the first chargeable means will be substantiallydissipated within the charge dissipating means.
 3. A circuit as claimedin claim 2, wherein the shaping means further comprises a circuit havingat least said one first chargeable electrical storage means connected soas to receive a charging current from a controlled source of electricityand become charged to a first voltage, thereby holding an effectivecharge; at least said one second chargeable means connected in parallelwith the pulse transforming means but in series with the meanspossessing effective inductance and also in series with the firstswitching means; the second chargeable means also being connected inparallel with the pulse transforming means; a discharging means inseries with the charge-dissipating means and in parallel with the firstchargeable means; and actuating means to control the switching means. 4.A circuit as claimed in claim 3, wherein the control means includesmeans to cause generation of each pulse to occur in a sequence and tominimize the risk of inadvertent generation of spurious pulses, saidcontrol means including means to control and monitor a source ofcharging current, means to monitor the amount of charge placed withinthe first chargeable means, together with means to initiate each pulsesubstantially as soon as the charge reaches a predetermined level, andmeans to cause a pulse to be generated after a certain time even if thepredetermined charge is not accomplished.
 5. A circuit as claimed inclaim 3, in which the first chargeable electrical storage meanscomprises at least one capacitor and has about twice the storagecapacity of the second chargeable electrical storage means, which alsocomprises at least one capacitor.
 6. A circuit as claimed in claim 3, inwhich the pulse transforming means is a transformer having aprimary:secondary turns ratio capable of providing pulses at aneffective output voltage and which pulse transforming means has anonconducting ferromagnetic core suitable for high-frequency use.
 7. Acircuit as claimed in claim 4, further including means to sense theinstantaneous phase of an alternating-current mains supply in order tolimit the initiation of charging to the zero-crossing intervals of thealternating-current mains supply and means to limit the initiation of apulse to those periods when the alternating-current mains supply link isof a polarity such that a rectification means placed between thealternating-current mains supply and a DC bus is in a reverse biasedstate during the generation of an output pulse.
 8. A circuit as claimedin claim 2, in which the charge dissipating means is a saturableinductor in series with an energy-dissipating means.
 9. A circuit asclaimed in claim 2, in which the charge dissipating means is provided asan intrinsic property of the pulse transforming means which is providedwith a saturable ferromagnetic core.
 10. A circuit as claimed in claim2, in which the charge dissipating means is a switch in series with anenergy-dissipating means.
 11. A circuit as claimed in claim 2, in whichfurther means to shape each pulse comprise one or more means to blockthe reverse flow of current and thereby minimize reversal of thepolarity of the waveform.